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a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 1 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 4gb nand flash h27u4g8_6f2d h27s4g8_6f2d *ba53f20d-240c* b34416/177.179.157.84/2010-10-08 10:08
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 2 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash document title 4 gbit (512m x 8 bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft jan. 12. 2010 preliminary 1.0 icc2: saparate cache case and normal case tcbsyw value update (5us-typ.) mar. 04. 2010 1.1 tcea -> tcr typo correction icc2 typcal delete (because of same as max. value) mar. 31. 2010 1.2 adding bad block marking information april 14. 2010 1.3 parameter page update fig. 37 correction at least five times -> 3 times in 3.21 june 29. 2010 1.4 typo correction d1 -> d in table. 29 oct. 8. 2010 *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 3 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash features summary density - 4gbit: 4096blocks nand flash interface - nand interface - address / data multiplexing supply voltage - vcc = 3.0/1.8v volt core supply voltage for program, erase and read operations. memory cell array - x8: (2k + 64) bytes x 64 pages x 4096 blocks - x16: (1k+32) words x 64 pages x 2048 blocks page size - x8: (2048 + 64 spare) bytes - x16:(1024 + 32spare) words block size - x8: (128k + 4k spare) bytes - x16:(64k + 2k spare) words page read / program - random access: 25us (max) - sequentiall access: 25ns / 45ns (3.0v/1.8v, min.) - program time(3.0v/1.8v): 200us / 250us (typ) - multi-page program time (2 pages): 200us / 250us (3.0v/1.8v, typ.) block erase / multiple block erase - block erase time: 3.5 ms (typ) - multi-block erase time (2 blocks): 3.5ms/ 3.5ms (3.0v/1.8v, typ.) sequrity - otp area - sreial number (unique id) - non-volatile protection option for otp and block0(opt.) - hardware program/erase disabled during power transition addtional feature - multiplane architecture : array is split into two independent planes. parallel operations on both planes are available, having program and erase time. - single and multiplane copy back program with automatic edc (error detection code) - single and multiplane page re-program - single and multiplane cache program - cache read - multiplane block erase reliability - 100,000 program / erase cycles (with 1bit /528byte ecc) - 10 year data retention onfi 1.0 compliant command set electronical signature - munufacture id: adh - device id package - lead/halogen free - tsop48 12 x 20 mm *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 4 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash contents 1 summary description ...................................................................................................................5 1.1 product list............................................................................................................... .....................6 1.2 pin description............................................................................................................ ....................8 1.3 functional block diagram................................................................................................... ............9 1.4 address role............................................................................................................... ..................10 1.5 command set................................................................................................................ ...............11 2 bus operations ............................................................................................................................13 2.1 command input.............................................................................................................. ..............13 2.2 address input.............................................................................................................. .................13 2.3 data input................................................................................................................. ...................13 2.4 data output................................................................................................................ .................13 2.5 write protect.............................................................................................................. ..................13 2.6 stand-by................................................................................................................... ...................13 3 device operation ...................................................................................................................14 3.1 page read.................................................................................................................. ..................14 3.2 data handiling restriction during program sequences......................................................................14 3.3 page program............................................................................................................... ................14 3.4 multiple plane program..................................................................................................... .............15 3.5 block erase................................................................................................................ ...................15 3.6 multiple plane block erase................................................................................................. .............16 3.7 copy-back program.......................................................................................................... .............16 3.8 multiple plane copy back program........................................................................................... ........17 3.9 special read for copy back................................................................................................. .............17 3.10 edc operation............................................................................................................. ...........17 3.11 read status register...................................................................................................... .............19 3.12 read status enhanced...................................................................................................... ...........19 3.13 read status register field definition..................................................................................... .........20 3.14 read edc status register.................................................................................................. ..........20 3.15 reset..................................................................................................................... ....................21 3.16 cache read................................................................................................................ ................21 3.17 cache program............................................................................................................. ..............22 3.18 multi-plane cache program................................................................................................. .........22 3.19 read id................................................................................................................... ...................24 3.20 read onfi signature....................................................................................................... ............26 3.21 read parameter page....................................................................................................... ...........26 3.22 parameter page data structure definition.................................................................................. ....26 4 other features .......................................................................................................................30 4.1 data protection and power on / off sequence................................................................................ ...30 4.2 ready/busy................................................................................................................. .................30 4.3 write protect (#wp) handling............... ................................................................................ .........30 5 device parameters ......................................................................................................................31 6 timing diagrams .........................................................................................................................35 7 package mechanical ...............................................................................................................58 7.1 power consumptions and pin capacitance for allowed stacking configurations.....................................59 8 application notes and comments .............................................................................................60 8.1 system interface using ce# don't care...................................................................................... ....60 8.2 system bad block replacement............................................................................................... .....61 8.3 bad block management system................................................................................................ ....62 *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 5 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 1 summary description h27(u_s)4g8_6f2d series is a 512mx8bit with spare 16mx8 bit capacity. the device is offered in 3.0/1.8 vcc power supply, and with x8 and x16 i/o interface its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 64 pages. memory array is split into 2 planes, each of them consisting of 2048 blocks. like all other 2kb - page nand flash devices, a program operation allows to write the 2112-byte page in typical 200us(3.3v) and an erase operation can be performed in typical 3.5ms on a 128k-byte block. in addition to this, thanks to multi-plan e architecture, it is possible to program 2 pages at a time (one per each plane) or to erase 2 blocks at a time (again, one per each plane ). as a consequence, multi-plane architecture allows program time to be reduced by 40% and erase time to be reduction by 50%. in case of multi-plane operation, there is small deg- radation at 1.8v application in terms of program/erase time. the multiplane operations are supported both with traditional and onfi 1.0 protocols. data in the page can be read out at 25ns (3v version) an d 45nsec (1.8v version) cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards different densit ies, without any rearrangement of footprint. commands, data and addresses are synchronously introduced using ce#, we#, ale and cle input pin. the on-chip program/erase controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. a wp# pin is available to provide hardware protection against program and erase operations. the output pin rb# (open drain buffer) signals the status of the device during each operation. in a system with multi- ple memories the rb# pins can be connected all together to provide a global status signal. each block can be programmed and erased up to 100,000 cycles with ecc (error correction code) on. to extend the life- time of nand flash devices, the implementation of an ecc is mandatory. the chip supports ce# don't care function. this function allo ws the direct download of the code from the nand flash memory device by a microcontroller, since the ce# transitions do not stop the read operation. in addition, device supports onfi 1.0 specification. the copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. copy back operation automatically executes embedded error detection operation: 1 bit error out of every 528-byte (x8) or 1 bit error out of every 264-word (x16) can be detected. with this feature it is no longer nec- essary to use an external to de tect copy back operation errors. multiplane copy back is also supported, both with traditiona l and onfi 1.0 protocols. data read out after copy back read (both for single and multiplane cases) is allowed. in addition, cache program and multi cache program operations improve the programing throughput by programing data using the cache register. the devices provide two innovative features: page re-program and multiplane page re-program. the page re-program allows to re-program one page. normally, this operation is performed after a previously failed page program operation. similarly, the multiplane page re-program allows to re-program two pages in parallel, one per each plane. the first page must be in the first plane while the second page must be in the second plane; the multiplane page re-program opera- tion is performed after a previously failed multiplane page program operation. the page re-program and multiplane *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 6 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash page re-program guarantee imporve performance, since data insertion can be omitted during re-program operations, and save ram buffer at the host in the case of program failure. the devices, available in the tsop48 (12x20mm) package, support the onfi1.0 specfication and come with four sequ- rity features: - otp (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permantely. - serial number (unique identifier), which allows the devices to be nuniquely indentified. - read id2 extention - non-volatile protection to lo ck sensible data permanently. these security features are subject to an nda (non-disclosure agreement) and are, therefore, no described in the datasheet. for more details about them, contact your nearest hynix sales office. 1.1.product list table 1: list of supported versions / packages part number organization operating range package h27u4g8f2d x8 2.7 to 3.6v - H27U4G6F2D x16 2.7 to 3.6v - h27s4g8f2d x8 1.7 to 1.95v - h27s4g6f2d x16 1.7 to 1.95v - vdd vss wp# cle ale re# we# ce# dq0~dq7 (x8) dq0~dq15 (x16) rb# fiur 1: li diara ba5f20-240 ivvywwtwtwwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 7 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash nc nc nc nc nc nc r/b re ce nc nc vcc vss nc nc cle ale we wp nc nc nc nc nc nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 12 13 37 36 25 48 1 24 nand flash tsop1 (x8) tabl 2: sial nas dq7 - dq0 data input / outputs (x8/x16) dq15 - dq8 data input / outputs (x16) cle command latch enable ale address latch enable ce# chip enable re# read enable we# write enable wp# write protect rb# ready/ busy v cc power supply v ss ground nc no connected internally nc nc nc nc nc nc r/b re ce nc nc vcc vss nc nc cle ale we wp nc nc nc nc nc vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 nc nc vcc nc nc nc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss 12 13 37 36 25 48 1 24 nand flash tsop1 (x16) g g figure 2. 48tsop1 contact, x8 and x16 devic *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 8 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 1.2 pin description pin name description dq0 - dq15 data inputs/outputs the dq pins allow to input command, address and da ta and to output data during read / program operations. the inputs are latched on the rising edge of write enable (we#). the i/o buffer float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the dq inputs inside the command register on the rising edge of write enable (we#). ale address latch enable this input activates the latching of the dq inputs inside the command register on the rising edge of write enable (we#). ce# chip enable this input controls the selection of the device. when the device is busy ce# low does not deselect the memory. we# write enable this input acts as clock to latch command, addres s and data. the dq inputs are latched on the rise edge of we#. re# read enable the re# input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re# which also increments the internal column address counter by one. wp# write protect the wp# pin, when low, provides an hardware prot ection against undesired modify (program / erase) operations. rb# ready busy the ready/busy output is an open drain pin that signals the state of the memory. v cc supply voltage for io buffer the v cc supplies the power for all the operations (read, write, erase). an internal lock circuit prevent the insertion of commands when v cc is less than v lko v ss ground nc / dnu no connected / don?t use table 3: pin description note: 1. a 0.1uf capacitor should be connected between the v cc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb trac k widths must be sufficient to carry the currents required during program and erase operations. 2. an internal voltage detector disables all functions whenever v cc is below 1.8v (3v version) or 1.1v (1.8v) version to protect the device from any invol untary program/erase during power transitions. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 9 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash command register io re# buffers y decoder page buffer x d e c o d e r 4096 mbit + 128 mbit nand flash memory array wp# ce# we# address register/ counter program erase controller hv generation command interface logic data register 1.3 functional block diagram figure 3: block description ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 10 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 1.4 address role table 4: address cycle map (x8) (*): a30 for 8gbit ddp(1ce). a30:a31 for 16gbit qdp(1ce). as far as the address bits are concerned, the following rules apply: a0 - a11 : column address in the page a12 - a17 : page address in the block a18 : plane address (for multi-plane operatio ns) / block address (for normal operations) a19 - a31 : block address table 5: address cycle map (x16) (*): a29 for 8gbit ddp(1ce). a29:a30 for 16gbit qdp(1ce) as far as the address bits are concerned, the following rules apply: a0 - a10 : column address in the page a11 - a16 : page address in the block a17 : plane address (for multi-plane operatio ns) / block address (for normal operations) a18 - a30 : block address dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 1 st cycle a0 a1 a2 a3 a4 a5 a6 a7 2 nd cycle a8 a9 a10 a11 0 0 0 0 3 rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4 th cycle a20 a21 a22 a23 a24 a25 a26 a27 5 th cycle (*) a28 a29 a30 a31 0 0 0 0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 1 st cycle a0 a1 a2 a3 a4 a5 a6 a7 2 nd cycle a8 a9 a10 0 0 0 0 0 3 rd cycle a11 a12 a13 a14 a15 a16 a17 a18 4 th cycle a19 a20 a21 a22 a23 a24 a25 a26 5 th cycle (*) a27 a28 a29 a30 0 0 0 0 *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 11 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 1.5 command set table 6: public command set command (1) 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle acceptable command during busy read 00h 30h read for copy-back 00h 35h special read for copy back 00h 36h read id 90h read id2 30h-65h-00h 30h reset ffh yes (2) page pgm (start) / cache pgm (end) 80h 10h cache pgm (start) / (continue) 80h 15h page reprogram / n th page cache reprogram (end) 8bh 10h n th page cache reprogram (continue) 8bh 15h n-1 th page cache reprogram (continue) 8ah 15h copy back pgm (start) 85h 10h (traditional) multi plane program (3) 80h 11h 81h 10h onfi multiplane program 80h 11h 80h 10h multiplane page re-program 8bh 11h 8bh 10h (traditional) multiplane cache pgm (start/cont) 80h 11h 81h 15h onfi multiplane cache pgm (start/cont) 80h 11h 80h 15h (traditional) multiplane cache pgm (end) (3) 80h 11h 81h 10h onfi multiplane cache pgm (end) 80h 11h 80h 10h n th pages multiplane cache re-program (cont) 8bh 11h 8bh 15h n th pages multiplane cache re-program (end) 8bh 11h 8bh 10h n-1 th pages multiplane cache re-program (cont) 8ah 11h 8ah 15h (traditional) multi plane copy back program (3) 85h 11h 81h 10h onfi multiplane copyback pgm 85h 11h 85h 10h block erase 60h d0h (traditional) multi plane block erase (3) 60h 60h d0h onfi multiplane block erase 60h d1h 60h d0h read status register 70h yes read status enhanced 78h yes random data input 85h random data output 05h e0h cache read(sequential) 31h cache read enhanced (random) 00h 31h cache read end 3fh read parameter page ech edc status read 7bh extended read status f2h/f3h/f4h/f5h yes *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 12 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash note: 1. commands listed in bold are referring to onfi 1.0 specification. 2. only during cache ready busy. 3.command maintained for backward compatibility table7: mode selection notes: 1. as 4gbit slc f41 is ce# don't care device, ce# high during latency time does no t stop the read operation. cle ale ce# we# re# wp# mode hllrisinghx read mode command input l h l rising h x address input hllrisinghh write mode command input l h l rising h h address input lllrisinghhdata input ll l (1) h falling x data output (on going) xx l (1) hhx data output (suspended) (2) lllhhxbusy time in read xxxxxhbusy time in program xxxxxhbusy time in erase xxxxxlwrite protect xxhxx 0 v / v cc stand by *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 13 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 2. bus operation there are six standard bus operationtable 28s that control the device. these are command input, address input, data input, data output, write prtable 28otect, and standby. (see figure 1 and table 6 ) typically glitches less than 5 ns on chip enable, write en able and read enable are ignored by the memory and do not affect bus operations. 2.1. command input command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/erase) the write protect pin must be high. see figure 5 and table 28 for details of the timings requirements. command codes are always applied on io7:0 regardless of the bus configuration. (x8 or x16) 2.2. address input address input bus operation allows the insertion of the memory address. 5 clock cycles are needed to input the addresses. addresses are accepted with chip enable low, address latch enable high, command latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify opera- tion (write/erase) the write protect pin must be high. see figure 5 and table 28 for details of the timings require- ments. addresses are always applied on io7:0 regardless of the bus configuration. (x8 or x16). refer to table 4 and table 5 for more detailed information. 2.3. data input data input bus operation allows to feed to the device the data to be programmed. the data insertion is serial and timed by the write enable cycles. data are accepted only with chip enable lo w, address latch enable low, command latch enable low, read enable high, and write protect hi gh and latched on the rising edge of write enable. see fig- ure 7 and table 28 for details of the timings requirements. 2.4. data output data output bus operation allows to re ad data from the memory array and to check the status register content, the edc register content and the id data. data can be serially sh ifted out by toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figure 8 to figure 11 and table 28 for details of the timings requirements. 2.5. write protect hardware write protection is activated when the write protect pin is low. in this condition modify operation do not start and the content of the memory is not altered. write protect pi n is not latched by write enable to ensure the protection even during the power up. 2.6. standby in standby the device is deselected, outputs are disabled and power consumption is reduced. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 14 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3. device operation 3.1. page read this operation is initiated by writing 00h and 30h to the command register along with five address cycles. two types of operations are available: random read, serial page read. the random read mode is enabled when the page address is changed. the 2112 bytes (x8) or 1056 (x16) of data within the selected page are transferred to the data registers in less than 25us(tr). the system controller may detect the comple tion of this data transfer (tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they ma y be read out in 25ns (3v version) and 45nsec (1.8v version) cycle time by sequentially pulsing re#. the repetitive high to low transitions of the re# clock make the device output the data starting from the se lected column address up to the last column address. the device may output random data in a page instead of the sequential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data output can be operated multiple times re gardless of how many times it is done in a page. after power up device is in read mode, so 00h command cycl e is not necessary to start a read operation. any operation other than read or random data output causes device to exit read mode. check figure 12, figure 13, figure 14 as references. 3.2 data handling restirctio ns during program sequences applications which use the error detection code in copy back must respect some restrictions related to data handling during program sequence. the error dection code check is used during copy back program and multiplane copy back program operations to detect single bit errors pccurred in the source page (for details about edc) note: the restrictions described below are not valid if the application uses the copy back program or multiplane copy back program without edc check. when data handling is performed, the page program, multiplane page program, page re-program, multiplane page re- program, cache ptrgram and multiplane cache program operations, must respect the following restrictions: 1. program operations must be performed on the whole page, or on the whple edc unit at a time. 2. for each program operation, random data input can be executed only once for each edc unit. copy back program or multiplane copy back program opeations must respect the following restrictions: 1. if rando, data input is applied in a given edc unit, the da ta of the whole edc unit must be inserted. in ohter words, the edc check is possible only if the whole edc unit is modified during a copy back program sequence. 2. for each program operation, rando, data input can be executed only once for each edc unit. 3.3 page program a page program cycle consists of a serial data loading period in which up to 2112 bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is pr ogrammed into the appropriate cell. the serial data loading period begins by inputting the serial data input command (80h), followed by the five cycle address inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input within a page. the column address of next data, which will be entered, may be changed to the address which follows random data input co mmand (85h). random data input may be operated multi- ple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the programming process. the internal write state controller automat- *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 15 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash ically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system con- troller for other tasks. once the program process starts, the read status register commands (70h or 78h) may be issued to read the status register. the system controller can detect the completion of a program cycle by monitoring the rb# output, or the status bit (i/o 6) of the status regi ster. only the read status commands (70h or 78h) or reset command are valid during programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked. the internal write verify detects only er rors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the com- mand register. figure 14 and figure 15 detail the sequence. the device is programmed basically by page, but it also allows multiple partial page programming of a word or consec- utive bytes up to 2112 (x8) or 1056 (x16) in a single page program cycle. the number of consecutive partial page programming operations (nop) within the same page must not exceed the number indicated in table 27 . in addition, pages must be sequentially programmed within a block. users which use "edc check" in copy back must comply with some limitations related to data handling during one page program sequence. please refer to section 3.10 for details. 3.4. multiple plane program device supports multiple plane program: it is possible to program 2 pages in parallel, one per each plane. a multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins with inputting the serial data input command (80h), followed by the five cycle address inputs and serial data for the 1 st page. address for this page must be in the 1 st plane (a<18>=0). the device supports random data input exactly same as in the case of page program operation. the dum- my page program confirm command (11h) stops 1 st page data input and devices becomes busy for a short time (t dbsy ). once it has become ready again, either the traditional " 81h" or the onfi 1.0 "80h" command must be issued, followed by 2 nd page address (5 cycles) and its serial data input. address for this page must be in the 2 nd plane (a<18>=1). program confirm command (10h) makes parallel programming of both pages to start. figure 20 and figure 21 de- scribe the sequences. user can check operation status by monitoring rb# pin or re ading status register commands (70h or 78h), as if it were a normal page program: read status register comma nd is also available during dummy busy time (t dbsy ). in case of fail in any of 1 st and 2 nd page program, fail bit of status register will be set however, in order to know which page failed, onfi 1.0 "read status enhanced" command must be issued refer to section 3.11 for further info. the number of consecutive partial page programming operations (nop) within the same page must not exceed the number indicated in table 27. in addition, it is recommended to program pages sequentially within a block. 3.5. block erase the block erase operation is done on a block basis. block address loading is accomplished in 3 cycles initiated by an erase setup command (60h). only addresses a18 to a29 are valid while a12 to a17 are ignored. the erase confirm command (d0h) following the block address loading initiates the internal erasing process this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we# after the erase confirm command input, the internal write controller handles erase and erase-verify. once the erase process starts, the read status register commands (70h or 78h) may be issued to read the status register. the system controller can detect the completion of an erase by monitoring the rb# output, or the status bit (i/o 6) of the status register. only the read status commands (70h or 78h) and reset command are valid while eras- ing is in progress. when th e erase operation is completed, the write status bit (i/o 0) may be checked. figure 19 details the sequence. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 16 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.6. multiple plane block erase multiple plane erase, allows parallel erase of two blocks in parallel, one per each memory plane. two different command sequences are allowed in these case, traditional and onfi 1.0. in traditional case, block erase setup command (60h) must be repeated two times, followed by 1 st and 2 nd block address respectively (3 cycles each). as for block erase, d0h command makes embedded operation to start. in this case, multiplane erase does not need any dummy busy time between 1 st and 2 nd block insertion. see figure 25 for details. as an alternative, the onfi 1.0 multiplane command protocol can be used, with 60h erase setup followed by 1 st block address and d1h first confirm, 60h erase setup followed by 2 nd block address and d0h (multi plane confirm). between the two block-related sequences, a short busy time t iebsy will occur. see table 27 and figure 26 for details. address limitation required for multiple plane program applies al so to multiple plane erase. also operation progress can be checked like in the multiple plane program through read status register, or onfi 1.0 read status enhanced. as for multiplane page program, the address of the first second page must be within the first plane (a18=0 for x8 devices, a17=0 for x16 devices) and second plane (a18 = 1 for devices, a17=1 for x16 devices), respectively. 3.7. copy-back program. the copy-back program is configured to quickly and efficiently rewrite data stored in one pa ge without utilizing an exter- nal memory. since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved. the benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also need to be copied to the newly assigned free block. the operation for performing a copy-back program is a sequential execution of page-read (without mandatory serial access) and copy back -program with the address of destina- tion page. a read operation with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer. as soon as the device returns to ready state, optional data read-out is allowed by toggling re# (see figure 17 ), or copy back command (85h) with the address cycles of destination page may be written. the program confirm command (10h) is required to actually begin the programming operation. source and destination page in the copy back program sequence must belong to the same device plane (x8 : same a18, x16 : same a17) data input cycle for modifying a portion or multiple distan t portions of the source page is allowed as shown in figure 18. this device includes automatic error detect ion code check during copy back operation, to detect single bit errors in edc units occurred in the source page. more details on edc operation, and limitation related to data input handling during one copy back program sequence are available in section 3.10 *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 17 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.8. multiple plane copy back program as for page program, device supports multi-plane copy back program with exactly same sequence and limitations. multi plane copy back program must be preceded by 2 single page read for copy back command sequences (1 st page must be read from the 1 st plane and 2 nd page from the 2 nd plane). multi-plane copy back cannot cross plane boundaries : the contents of the source page of one device plane can be cop- ied only to a destination page of the same plane. edc check is available also for multi-plane copy back program. users which use "edc check" in copy back must comply with some limitations related to da ta handling during one multi- plane copy back program sequence. please refer to section 3.10 for details. also in this case, two different sequences are allowed : th e traditional one (85h, first plane address 11h, 81h, second plane address, 10h) represented in figure 22 , and onfi 1.0 sequence (85h, first plane address 11h, 85h, second plane address, 10h) represented in figure 23 and figure 24 . 3.9. special read for copy back the device feature the "special read for copy back". if copy back read (described in sections 3.7 and 3.8 ) is triggered with confirm command "36h" instead "35h", copy back read from target page(s) will be executed with an increased internal (vpass) voltage. this special feature is used in order to try to recover incorrigi ble ecc read errors due to over-program or read disturb: it shall be used only if ecc read errors have occurred in the source page using "standard read" or "standard read for copy back" sequences.. excluding the copy-back read confirm command, all other features described in sections 3.7 and 3.8 for standard copy back remain valid (including the figures referred to in those sections). 3.10. edc operation error detection code check is a feature which be used du ring copy back program operation (both single and multi- plane) to detect single bit errors occurred in the source page (s). - in the x8 version edc check allows detection of up to 1 si ngle bit error every 528 bytes, where each 528 byte group is composed by 512 byte of main array and 16 bytes of spare area (see table 8 and table 9 ). the described 528 byte area is called "edc unit". - in the x16 version edc allows detection of up to 1 single bit error every 264 words, where each 264 word group is composed by 256 words of main array and 8 words of spare area (see table 10 and table 11 ). the described 264 word area is called "edc unit". edc result can be checked through specific read edc register command, available only during copy back program and only for the device version supporting ecc=1. edc register can be queried during the copy back program busy time. (t prog) for "edc check" feature to operate correctly specific conditions on data input handling apply for page program and copy back program (single, cached, multi-plane): *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 18 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash for the case of page program 1) in section 3.2 it was explained that a number of consecutive partial program operations (nop) is allowed within the same page. in case this feature is used, the number of partial program operations occurring in the same edc unit must not exceed "one" (1). in other words, page program operations must be performed on the whole page, or on whole edc unit at a time. 2) "random data input" in a given edc unit can be executed several times during one page program sequence, but data insertion in each column address of each edc unit must not exceed "one" (1). for the case of copy back program 1) if random data input is applied in a given edc unit, the data of the whole edc unit must be inserted. in other words, the edc check is possible only if the whole edc unit is modified during one copy back program sequence 2) "random data input" in a given edc unit can be executed several times during one copy back sequence , but data insertion in each column address of the edc unit must not exceed "one" (1) for the user which use copy back without edc check, all the limitations described above do not apply. table 8: page organization in edc units (x8) table 9: page organization in edc units (x8) table 10: page organization in edc units (x16) table 11: page organization in edc units (x16) ?a?area (1 st sector) ?b?area (2 nd sector) ?c?area (3 rd sector) ?d?area (4 th sector) ?e?area (1 st sector) ?f?area (2 nd sector) ?g?area (3 rd sector) ?h?area (4 th sector) 512 byte 512 byte 512 byte 512 byte 16 byte 16 byte 16 byte 16 byte sector main field (column 0~2047) spare field (column 2048~2111) area name column address area name column address 1 st 528-byte sector ?a? 0~511 ?e? 2048~2063 2 nd 528-byte sector ?b? 512~1023 ?f? 2064~2079 3 rd 528-byte sector ?c? 1024~1535 ?g? 2080~2095 4 th 528-byte sector ?d? 1536~2047 ?h? 2096~2111 ?a?area (1 st sector) ?b?area (2 nd sector) ?c?area (3 rd sector) ?d?area (4 th sector) ?e?area (1 st sector) ?f?area (2 nd sector) ?g?area (3 rd sector) ?h?area (4 th sector) 256 words 256 words 256 words 256 words 8 words 8 words 8 words 8 words sector main field (column 0~1023) spare field (column 1024~1055) area name column address area name column address 1 st 264-word sector ?a? 0~255 ?e? 1024~1031 2 nd 264-word sector ?b? 256~511 ?f? 1032~1039 3 rd 264-word sector ?c? 512~767 ?g? 1040~1047 4 th 264-word sector ?d? 768~1023 ?h? 1048~1055 main field (2,048 byte) spare field (64 byte) *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 19 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.11 read status register. the device contains a status register to retrieve the status value for the last operation issued. after writing 70h command to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce# or re#, whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when rb# pins are common-wired. refer to table 12 for specific status register definition, and to figure 10 and figure 38 for timings. if read status register command is issued during multi-plan e operations read status register polling shall return the combined status value related to the outcome of the operation in the two planes according to this table: status register is dynamic in other words, user is not required to toggle re# / ce# to update it. the command register remains in status read mode until further commands are issued. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. note: read status register command shall not be used for concurrent operations in of multi-dice stack configurations (single ce#). for this case, either "read status enhanced" ( section 3.12 ) shall be used instead. 3.12 read status enhanced read status enhanced is an additional feature used to retrieve the status value for a previous operation in the following cases: - on a specific die of a multi-dice stack configurations (single ce#), in case of concurrent operations when 4gbit dice are stacked(*) to form 8gbit ddp or 16gbit qdp (single ce#), it is possible to run a first operation on the first 4gbit, then activate a concurrent operation on th e second (or third or fourth) device. (examples: erase while read, read while program, etc.) - on a specific plane in case of mult i-plane operations in the same die. figure 39 defines the read status enhanced be havior and timings. the plane and die address must be specified in the command sequence in order to retrieve the status of the die and the plane of interest. refer to table 12 for specific status register definition. the command register remains in status read mode until further commands are issued. status register is dynamic in other words, user is not required to toggle re# / ce# to update it. status register bit composite status value bit 0, pass/fail or bit 1, cache pass/fail or *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 20 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.13 read status register field definition table 12 below lists the meaning of each bit of read status register and read status enhanced table 12: status register coding 3.14 read edc status register this operation is available only in copy back program and it allows the detection of errors occurred during read for copy back. in case of multiple plane copy back, it is not possible to know which of the two read operation caused the error. after writing read edc status register command (7bh) to th e command register, a read cycle outputs the content of the edc register to the i/o pins on the falling edge of ce# or re#, whichever occurs last. operation is same as read status register command. refer to table 13 for specific edc register definitions: io page program/ page reprogram block erase read cache read cache program/ cache reprogram coding 0 pass / fail pass / fail na na pass / fail n page pass: ?0? fail: ?1? 1na na na na pass / fail n - page pass: ?0? fail: ?1? 2na na na na na - 3na na na na na - 4na na na na na - 5 ready / busy ready / busy ready / busy ready / busy ready / busy active: ?0? idle: ?1? 6 ready / busy ready / busy ready / busy ready / busy ready / busy data cache read/busy busy: ?0? ready: ?1? 7 write protect write protect write protect write protect write protect protected: ?0? not protected: ?1? table 13: edc register coding io copy back program coding 0 pass / fail pass: ?0? fail: ?1? 1 edc status no error: ?0? error: ?1? 2 edc validity invalid: ?0? valid: ?1? 3na - 4na - 5 ready / busy busy: ?0? ready: ?1? 6 ready / busy busy: ?0? ready: ?1? 7 write protect protected: ?0? not protected: ?1? *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 21 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.15 reset the device offers a reset feature, executed by writing ffh to the command register. if the device is in busy state during random read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp# is high. refer to table 16 for device status after reset operation. if the device is already in re set state a new reset command will not be accepted by the com- mand register. the rb# pin transitions to low for t rst after the reset command is written. refer to figure 28 for further details. 3.16 cache read cache read can be used to increase the read operation speed, as defined in section 3.1 , which is available only within a block. as soon as the user starts to read one page, the de vice automatically loads the next page into the cache register. serial data output may be executed while data in the memory is read into cache register, cache read is initiated by the page read sequence (00-30h) on a page m. after random access to the first page is complete (r/b# returned to high, or read status register io<6> switches to high), two command sequences can be used to continue read cache: - sequential read cache continue (command "31h" only): once the command is latched into the command register (see figure 30 ), device does busy for a short time (t rcbsy ), during which data of the first page is transferred from the data register to the cache register. at the end of this phase cach e register data can be output by toggling re# while the "next "page (page address m+1) is read from the memory array into data register. - random read cache continue (sequence "00h" "31"): once the command is latched into the command register (see figure 31 ), device does busy for a short time (t rcbsy ), during which data of the first page is transferred from the data register to the cache register. at the end of this phase cache register data can be output by toggling re# while page n is read from the memory array into data register. subsequent pages are read by issuing additional "sequential" or "random" read cache continue command sequences. if serial data output time of one page exceeds random access time (t r ), the random access time of the next page is hidden by data downloading of the previous page. on the other hand, if 31h is issued prior to complete the rand om access to the next page, the device will stay busy as long as needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the following page. to terminate cache read, 3fh command should be issued (see figure 32 ). this command transfer data from data reg- ister to the cache register without issuing next page read. during the cache read operation, device doesn't allow any ot her command except for 31h, 3fh, read sr or reset (ffh). to carry out other operations cache read must be ended either by 3fh command or device must be reset by issuing ffh. read status command (70h) may be issued to check the status of the different registers, and the busy/ready status of the cached read operations. more in detail: a) the cache-busy status bit i/o<6> indicates when the cache register is ready to output new data. b) the status bit i/o<5> can be used to determine when the ce ll reading of the current data register contents is complete. note: 31h and 3fh commands reset the column counter thus when re# is toggled to output the data of a given page, the first output data is related to the first byte of the page (column address 00h). random data output command can be used to switch column address. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 22 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.17 cache program cache program is used to improve the program throughput by programing data using the cache register. the cache pro- gram operation can only be used within one block. the cache register allows new data to be input while the previous data that was transffered to th e page buffer is programmed into the memory array. cache program is available only within a block after the serial data input command (80h) is loaded to the co mmand register, followed by 5 cycles of address, a full or partial page of data is latched into the cache register. once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data register for cell programming. at this time the devi ce remains in busy state for a short time (tcbsyw). after all data of the cache register are transferred into the data register, the device return s to the ready state, and allows loading the next data into the cache register through another cache program command sequence (80h-15h). the busy time following the first sequence 80h - 15h equals the time needed to transfer the da ta of cache register to the data register. cell programming of the data of data register and loading of the next data into the cache register is conse quently processed through a pipeline model. in case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming of current data register contents is complete: till this moment the device will stay in a busy state (tcbsyw). read status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the cached program operations. more in detail: a) the cache-busy status bit i/o<6> indicates when the cache register is ready to accept new data. b) the status bit i/o<5> can be used to determine when th e cell programming of the current data register contents is complete. c) the cache program error bit i/o<1> can be used to identify if the previous page (page n-1) has been successfully programmed or not in cache program operation. the latte r can be polled upon i/o<6> status bit changing to "1" . d) the error bit i/o<0> is used to identify if any error has been detected by the program / erase controller while program ming page n. the latter can be polled upon i/o<5> status bit changing to "1". i/o<1> may be read together with i/o<0>. if the system monitors the progress of the operation only wi th r/b#, the last page of the target program sequence must be programmed with page program confirm command (10h). if the cache program command (15h) is used instead, the status bit i/o<5> must be polled to find out if the last programming is finished before starting any other operation. see table 12 and figure 40 for more details. 3.18 multi-plane cache program the device supports multi-plane cache program, which enables high program throughput by programming two pages in parallel while exploiting the data and cache registers of both planes to implement cache. the device supports both the trad itional and onfi 1.0 command sets. the command sequence can be summarized as follows: a) serial data input command (80h), followed by the fi ve cycle address inputs and then serial data for the 1 st page. ad dress for this page must be within 1 st plane (a<20>=0). the data of 1 st page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. b) the dummy page program confirm command (11h) stops 1 st page data input and the device becomes busy for a short time (t dbsy ). c) once device returns to ready again, 81h (or 80h) command must be issued, followed by 2 nd page address (5 cycles) and its serial data input. address for this page must be within 2 nd plane (a<20>=1). the data of 2 nd page other than those to be programmed do not need to be loaded. d) cache program confirm command (15h) once the cache write command (15h) is loaded to the command register, the *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 23 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash data in the cache registers is transferred into the data registers for cell programming. at this time the device remains in bus y state for a short time (tcbsyw). after all data of the cache registers are transferred into the data registers, the device retu rns to the ready state, and allows loading the next data into the cache register through another cache program command se quence. the sequence 80h-...- 11h...-...81h...-...15h (or the corresponding onfi 80h-...- 11h...-...80h...-...15h ) can be iterated, a nd any new time the device will be busy for a for the tcbsyw time needed to complete cell programming of current data registers contents, and transfer from cache registers can be allowed. the sequence to end multi-plane cache program is 80h-...- 11h...-...81h...-...10h (or 80h-...- 11h...-...80h...-...10h for the onfi 1.0 case). figure 50 and figure 51 show the command sequence for the multi plane cache program operation for the two protocols. multi-plane cache program is available only within two paired blocks belonging to the two planes.. user can check operation status by r/b# pin or read status register commands (70h or 78h) if user opts for 70h, status register read will provide a "global" information about the op eration in the two planes. more in detail: a) i/o<6> indicates when both cache registers are ready to accept new data. b) i/o<5> indicates when the cell programming of the current data registers is complete c) i/o<1> identifies if the previous pages in both planes (pages n-1) have been successfully programmed or not. the latter can be polled upon i/o<6> status bit changing to "1". d) i/o<0> identifies if any error has been detected by the program / erase controller while programming the two pages n. the latter can be polled upon i/o<5> status bit changing to "1". see table 12 for more details if the system monitor rs the progress of the operation only with r/b#, the last pages of the target program sequence must be programmed with page program confirm command (10h). if the cache program command (15h) is used instead, the sta tus bit i/o<5> must be polled to find out if the last pr ogramming is finished before starting any other operation. refer to section 3.11 for further information. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 24 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3.19 read id. the device contains a product identification mode, initia ted by writing 90h to the command register, followed by an address input of 00h. the 5-byte read id configuration are supported: the device operating mode (5-byte) is selected through cam setting. 3.19.1 legacy read id five read cycles sequentially output the manufacturer code (20h), and the device code and 3 rd , 4 th , and 5 th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 27 shows the operation sequence, while table 14 to table 18 explain the byte meaning. complete read id code table is as follows. table 14: legacy " read id for supported configurations note: for 1.8v version, io<7,3>=00 would mean "50nsec", while device serial cycle time is 45nsec table 15: "legacy" read id bytes meaning density org vcc 1 st 2 nd 3 rd 4 th (1) 5 th 4 gbit x8 3.0v adh dch 90h 95h 54h x16 3.0v adh cch 90h d5h 54h x8 1.8v adh ach 90h 15h 54h x16 1.8v adh bch 90h 55h 54h 8 gbit ddp x8 3.0v adh d3h d1h 95h 58h x16 3.0v adh c3h d1h d5h 58h x8 1.8v adh a3h d1h 15h 58h x16 1.8v adh b3h d1h 55h 58h 16 gbit qdp x8 3.0v adh d5h d2h 95h 5ch x16 3.0v adh c5h d2h d5h 5ch x8 1.8v adh a5h d2h 15h 5ch x16 1.8v adh b5h d2h 55h 5ch device identifier byte description 1 st manufacturer code 2 nd device identifier 3 rd internal chip number, cell type, etc. 4 th page size, block size, spare size, organization 5 th multiplane information *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 25 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 3 rd id data table 16: legacy read id 3 rd byte description 4 th id data table 17: legacy read id 4 th byte description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size (byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 26 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 5 th id data table 18: legacy read id 5 th byte description 3.20 read onfi signature to retrieve the onfi signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an address of 00h and read 36 bytes to get the onfi signature). the onfi signature is the ascii encoding of 'onfi' where 'o' = 4fh, 'n' = 4eh, 'f' = 46h , and 'i' = 49h. reading beyond four bytes yields indeterminate values. figure 28 shows the operation sequence 3.21 read parameter page the read parameter page function retrieves the data structur e that describes the chip's organization, features, timings and other behavioral parameters. figure 37 defines the read parameter page behavior. this data structure enables the host processor to automatica lly recognize the nand flash configuration of a device. the whole data structure is repeated at leat three times. the random data read command can be issued during execut ion of the read parameter page to read specific portions of the parameter page. the read status command may be used to check the status of read parameter page during execution. after completion of the read status command, 00h is issued by the host on th e command line to continue with the data output flow for the read parameter page command. read status enhanced shall not be used during execution of the read parameter page command. 3.22 parameter page data structure definition table21 defines the parameter page data structure. for paramete rs that span multiple byte s, the least significant byte of the parameter corresponds to the first byte. values are reported in the parameter page in units of bytes wh en referring to items related to the size of data access (as in an 8-bit data access device). for example, the chip will return how many data bytes ar e in a page. for a device that supports 16-bit data access, the host is required to convert byte values to word values for its use. unused fields should be cleared to 0h. for more detailed information abou t parameter page data bits, refer to onfi specification 1.0 section 5.4.1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 27 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, "o" byte 1: 4eh, "n" byte 2: 46h, "f" byte 3: 49h, "i" 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd to even page copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width h27u4g8f2dka-bm :1ch, 00h h27s4g8f2dka-bm :1ch, 00h h27s4g6f2dka-bm :1dh, 00h h27u4g8f2dtr-bc :1ch, 00h h27u4g8f2dtr-bi :1ch, 00h h27u8g8g5dtr-bc :1ch, 00h h27u8g8g5dtr-bi :1ch, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports read status enhanced 2 1 = supports get features and set features 1 1 = supports read cache ntegrit 0 1 = supports page cache program command 1bh, 00h 10-31 reserved (0) 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 48h, 59h, 4eh, 49h, 58h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) h27u4g8f2dka-bm 48h, 32h, 37h, 55h, 34h, 47h, 38h, 46h, 32h, 44h, 4bh, 41h, 2dh, 42h, 4dh, 20h, 20h, 20h, 20h, 20h h27s4g8f2dka-bm 48h, 32h, 37h, 53h, 34h, 47h, 38h, 46h, 32h, 44h, 4bh, 41h, 2dh, 42h, 4dh, 20h, 20h, 20h, 20h, 20h h27s4g6f2dka-bm 48h, 32h, 37h, 53h, 34h, 47h, 36h, 46h, 32h, 44h, 4bh, 41h, 2dh, 42h, 4dh, 20h, 20h, 20h, 20h, 20h h27u4g8f2dtr-bc 48h, 32h, 37h, 55h, 34h, 47h, 38h, 46h, 32h, 44h, 54h, 52h, 2dh, 42h, 43h, 20h, 20h, 20h, 20h, 20h h27u4g8f2dtr-bi 48h, 32h, 37h, 55h, 34h, 47h, 38h, 46h, 32h, 44h, 54h, 52h, 2dh, 42h, 49h, 20h, 20h, 20h, 20h, 20h h27u8g8g5dtr-bc 48h, 32h, 37h, 55h, 38h, 47h, 38h, 47h, 35h, 44h, 54h, 52h, 2dh, 42h, 43h, 20h, 20h, 20h, 20h, 20h h27u8g8g5dtr-bi 48h, 32h, 37h, 55h, 38h, 47h, 38h, 47h, 35h, 44h, 54h, 52h, 2dh, 42h, 49h, 20h, 20h, 20h, 20h, 20h 64 m jedec manufacturer id adh 65-66 o date code 00h 67-79 reserved (0) 00h *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 28 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 40h, 00h 86-89 m number of data bytes per partial page 00h, 02h, 00h, 00h 90-91 m number of spare bytes per partial page 10h, 00h 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logical unit (lun) 00h, 10h, 00h, 00h 100 m number of logical units (luns) 01h 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles 23h 102 m number of bits per cell 01h 103-104 m bad blocks maximum per lun 50h, 00h 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 00h, 00h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 reserved 0 1 = partial page programming has constraints 00h 112 m number of bits ecc correctability 01h 113 m number of interleaved address bits 4-7 reserved (0) 0-3 number of interleaved address bits 01h 114 o interleaved operation attributes 4-7 reserved (0) 3 address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 overlapped / concurrent interleaving support 04h 115-127 reserved (0) 00h electrical parameters block 128 m i/o pin capacitance 0ah 129-130 m timing mode support 6-1 5reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 h27u4g8f2dka-bm :1fh, 00h h27s4g8f2dka-bm :03h, 00h h27s4g6f2dka-bm :03h, 00h h27u4g8f2dtr-bc :1fh, 00h h27u4g8f2dtr-bi :1fh, 00h h27u8g8g5dtr-bc :1fh, 00h h27u8g8g5dtr-bi :1fh, 00h *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 29 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash ?o? stands for optional, ?m? for mandatory 131-132 o program cache timing mode support 6-1 5reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, h27u4g8f2dka-bm :1fh, 00h h27s4g8f2dka-bm :03h, 00h h27s4g6f2dka-bm :03h, 00h h27u4g8f2dtr-bc :1fh, 00h h27u4g8f2dtr-bi :1fh, 00h h27u8g8g5dtr-bc :1fh, 00h h27u8g8g5dtr-bi :1fh, 00h 133-134 m t prog maximum page program time ( ) bch, 02h 135-136 m t bers maximum block erase time ( ) 0ah, 00h 137-138 m t r maximum page read time ( ) 19h, 00h 139-140 m t ccs minimum change column setup time (ns) 64h, 00h 141-163 reserved (0) 00h vendor block 164-165 m vendor specific revision number 00h 166-253 vendor specific 00h 254-255 m integrita crc h27u4g8f2dka-bm :48h, f6h h27s4g8f2dka-bm :9bh, ceh h27s4g6f2dka-bm :54h, 61h h27u4g8f2dtr-bc :1fh, edh h27u4g8f2dtr-bi :5bh, 14h h27u8g8g5dtr-bc :fch, c1h h27u8g8g5dtr-bi :b8h, 38h redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundant parameter pages ffh *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 30 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 4. other features 4.1 data protection and power on / off sequence the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal volt- age detector disables all functions whenever vcc is below about 1.8v (3v version), or 1.1v (1.8v version). the power-up and power-down sequence is shown in figure 32 in this case v cc and v ccq on the one hand (and vss and v ssq on the other hand) are shorted together at all times the ready/busy signal shall be valid within 100us since the power supplies have reached the minimum values (as spec- ified on), and shall return to one within 5msec (max). during this busy time, the device executes the initializatio n process (cam reading), and dissipates a current icc0 (30ma max) in addition, it disregards all command excluding read status register (70h). at the end of this busy time, the device deaults into "read setup", thus if user decides to issue page read command, the 00h command may be skipped. wp# pin provides hardware protection and is recommended to be kept at vil during power-up and power-down. a re- covery time of minimum 100usec is required before internal circuit gets ready for any command sequences as shown in figure 33 . the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the completion of a page program, erase, copy- back, random read completion. the rb# pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more rb# outputs to be or-tied. because pull-up resistor value is related to tr(rb#) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart ( refer to figure 34 ). its value can be determined by the following guidance. 4.3 write protect (#wp) handling erase and program operations are aborted if wp# is driven low during busy time, and kept low for about 100nsec. switching wp# low during this time is eq uivalent to issuing a reset command (ffh) the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the r/b# pin will stay low for t rst (similarly to figure 29 ). at the end of this time, the command register is ready to process the next command, and the status register bit io<6> will be cleared to "1", while io<7> value will be related to the wp# value. refer to table 12 for more information on device status. erase and program operations are enabled or disabled by setting wp# to high or low respectively prior to issuing the set- up commands (80h or 60h). the level of wp# shall be set tww nsec prior to raisin g the we# pin for the set up command, as explained in f igure 35 and figure 36 .
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 31 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash we io[7:0] wp valid > 100nsec sequence aborted figure 5: wp# low timing reuirements during program/erase command seuence 5. device parameters table 22: valid blocks number (*) each 4gb has maximum 80 bad blocks note: the 1st block is quranteed to be a valid blick at the time of shipment. table 23: absolute maximum ratings notes: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in th e operating sections of this sp ecification is not implied. expo sure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmi croelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to -2v during tran sition and for less than 20ns during transitions. parameter symbol min typ max unit valid block numbe, 4gb n vb 4016 - 4096 blocks valid block numbe, 8gb n vb 8032(*) - 8192 blocks valid block numbe, 16gb n vb 16064(*) - 16284 blocks symbol parameter value unit 3.0 t a ambient operating temperature (temperature range option 1) 0 to 70 c ambient operating temperature (temperature range option 6) -40 to 85 c t bias temperature under bias -50 to 125 c t stg storage temperature -60 to 150 c v io (2) input or output voltage -0.6 to 4.6 v v cc supply voltage -0.6 to 4.6 v *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 32 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash table 24: dc and operating characteristics notes: 1) all v ccq and vcc pins, and vss and vssq pins respectively are shorted together 2) values listed in this table refer to the complete voltage range for v cc and v ccq and to a single device in case of device stacking refer to section 7.3 3) all current measurement are performed with a 0.1uf capacitor connected between the vcc supply voltage pin and the vss ground pin. 4) standby current measurement can be performed after the device has completed the initialization process at power up. refer to section 4.1 for more details table 25: ac test conditions parameter symbol test conditions 1.8volt 3.0volt unit min typ max min typ max power on current i cc0 power up current (refer to 4.41) - 15 30 - 15 30 ma operatin g current sequential read i cc1 t rc = see table 28 ce#=v il, i out =0ma - 10 20 - 15 30 ma program i cc2 normal - - 20 - - 30 ma cache - - 30 - - 40 ma erase i cc3 - - 10 20 - 15 30 ma stand-by current (ttl) i cc4 ce#=v ih , wp#=0v/vcc --1--1ma stand-by current (cmos) i cc5 ce#=vcc-0.2, wp#=0/vcc - 10 50 - 10 50 ua input leakage current i li v in =0 to 3.6v -- 10 -- 10 ua output leakage current i lo v out =0 to 3.6v -- 10 -- 10 ua input high voltage v ih - vcc *0.8 - vcc +0.3 vcc *0.8 - vcc +0.3 v input low voltage v il --0.3- vcc- *0.2 -0.3 - vcc *0.2 v output high voltage level v oh i oh = -100ua vcc- 0.1 -----v i oh = -400ua -- -2.4---v output low voltage level v ol i oh = -100ua --0.1- -v i ol = 2.1ma -- - --0.4v output low current (rb#) i ol (rb#) v ol = 0.1v 3- 4 ---ma v ol = 0.4v -- -8-10ma parameter value 1.8volt 3.0volt input pulse levels 0v to vcc 0v to vcc input rise and fall times 5ns 5ns input and output timing levels vcc / 2 vcc / 2 output load (1.7v - 1.95volt & 2.7v-3.6v) 1 ttl gate and cl=30(1.8v), 50pf(3.3v) 1 ttl gate and cl=30(1.8v), 50pf(3.3v) *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 33 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash table 26: pin capacitance (ta = 25c, f=1.0mhz) note: for the stacked devices versio n the input capacitance is 10pf x (number of stacked chips) and the i/o ca pacitance is 10pf x (number of stacked chips) table 27: program / erase characteristics note: typical program time is defined as the time within which more than 50% of the whole pages are programmed (vcc=3.3v and 1.8v, 25*c ) item symbol test condition min max unit input / output capacitance (1) c i/o v il = 0v -10pf input capacitance (1) c in v in = 0v -10pf parameter symbol min typ max unit program time / multi-plane program time (3.0v) t prog - 200 700 us program time/ multi-plane program time (1.8v) - 250 700 us dummy busy time for two plane program t dbsy -0.51us cache program short busy time t cbsyw -5 t prog us number of partial program cycles in the same page main + spare array nop - - 4 cycle block erase time / multi-plane erase time (3.0v) t bers -3.510ms block erase time/ multi-plane block erase time (1.8v) t bers -3.510ms read cache busy time tcbsyr - 3 tr us multi-plane erase short busy time (onfi protocol only) t iebsy -0.51us *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 34 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash table 28: ac timing characteristics notes: 1. the time to ready depends on the value of the pull-up resistor tied to rb# pin 2. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5us parameter symbol 1.8 volt 3.0 volt unit min max min max cle setup time t cls 25 12 ns cle hold time t clh 10 5 ns ce# setup time t cs 35 20 ns ce# hold time t ch 10 5 ns we# pulse width t wp 25 12 ns ale setup time t als 25 12 ns ale hold time t alh 10 5 ns data setup time t ds 20 12 ns data hold time t dh 10 5 ns write cycle time t wc 45 25 ns we# high hold time t wh 15 10 ns address to data loading time t adl 100 70 ns data transfer from cell to register t r 25 25 us ale to re# delay t ar 10 10 ns cle to re# delay t clr 10 10 ns ready to re# low t rr 20 20 ns re# pulse width t rp 25 12 ns we# high to busy t wb 100 100 ns read cycle time t rc 45 25 ns re# access time t rea 30 20 ns ce# low to re# low t cr 10 10 ns re# high to output hi-z t rhz 100 100 ns ce# high to output hi-z t chz 30 30 ns ce# high to ale or cle don't care t csd 10 10 ns re# high to output hold t rhoh 15 15 ns re# low to output hold t rloh -5 ns ce# high to output hold t coh 15 15 ns re# high hold time t reh 15 10 ns output hi-z to re# low t ir 00 ns re# high to we# low t rhw 100 100 ns we# high to re# low t whr 60 60 ns device resetting time(read/program/erase) t rst - 5/10/500 (2) 5/10/500 (2) ns write protection time t ww 100 100 ns *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 35 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash tcl s tcs twp command cle ce we ale i/o x tdh tds tals talh tclh tch w&/6 w&6 w:& w$/6 w$/6 w$/6 w$/6 w$/6 w$/+ w$/+ w$/+ w$/+ w$/+ w:& w:& w:& w:3 w:3 w:+ w:3 w:3 w:+ w:+ w:+ w'6 &ro$gg &/( &( :( $/( ,2[ &ro$gg 5rz$gg 5rz$gg 5rz$gg w'6 w'6 w'6 w'6 w'+ w'+ w'+ w'+ w'+ 6. timing diagrams command latch cycle figure 5: command latch cycle address latch cycle figure 6: address latch cycle *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 36 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash twc tclh tch twp twh din 1 din final twh tdh tdh tdh tds tds tds twp twp cle ale ce i/ox we tals din 0 trc ce re i/ox r/b trea trr dout dout dout trea trhz trhz trea tchz tcoh trhoh treh notes: transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. trloh is valid when frequency is higher than 33mhz. trhoh starts to be valid when frequency is lower than 33mhz. * serial access cycle after read (cle=l, we =h, ale=l) figure 8: sequential out cycle after read *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 37 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash tcls t clr t clh t cs t ch t wp t whr t cea t ds t rea t chz t coh t rhz t rhoh 70h or 7bh status output t dh t ir ce we iox cle re status read cycle & edc status read cycle trc trp treh trea tcr trloh trr trea tchz tcoh trhz trhoh dout dout ce re iox r/b serial access cycle after read (edo type, cle=l, we=h, ale=l) notes: transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. trloh is valid when frequency is higher than 33mhz. trhoh starts to valid when frequency is lower than 33mhz. figure 9: sequential out cycle after read figure 10: status / edc read cycle ba53f20d-20c iz[[]vuuu[vywwtwtwgwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 38 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cle ale we io0-7 re 78h r1 r2 r3 sr figure 11: read status enhanced cycle read operation figure 12: read operation (read one page) ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 39 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash read operation (intercepted by ce ) figure 13: read operation intercepted by ce# random data output in a page figure 14: random data output *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 40 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cle ale ce re r/b i/ox we twc serial data input command column address notes: tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. row address read status command program command i/o0=0 successful program i/o0=1 error in program 1 up to m byte serial input din n din m twc twb tprog twhr twc tadl 80h col. add1 col. add2 row. add1 row. add2 10h 70h i/o0 row. add3 page program operation figure 15: page program operation page program operation with random data input figure 16: random data in cle ale ce re r/b iox we 80h din n din m din j din k 85h 10h 70h serial data input command random data input command column address column address serial input program command read status command tprog io0 twb col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 tadl column address twc twc tadl twc twhr notes : 1. tadl is the time from the we risinig edge of final address cycle to the we rising edge of first data cycle. 2. for edc operation. only one time random data input is possible at same address. ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 41 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash figure 17: copy back read with optional data readout copy- back program operation with random data input figure 18: copy back program with random data input *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 42 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash twc cle ce we ale re iox r/b twb tbers busy auto block erase setup command io0=0 successful erase io0=1 error in erase row address d0h 60h 70h i/o0 erase command read status command row add1 row add2 row add3 twhr block erase operation figure 19: block erase operation (erase one block) two-plane page program operation notes: 1) the figure refers to x8 case. please refer to section 1.4 for address remapping rules for the x16 case 2) any command between 11h and 81h is prohibited except 70h, 78h and ffh figure 20: multiple plane page program (traditional protocol) cle ale ce re r/b i/ox we r/b io ex.) tow-plane page program 81h 70h io program confirm command (true) tdbsy: typ. 500us max. 1us tdbsy col add 1,2 & row add 1,2,3 2112 byte data) a0 ~ a11 : valid a12 ~ a17 : fixed low a18 : fixed low a19 ~ a28 : fixed low serial data input command column address page row address 1 up to 2112 byte data serial input program command (dummy) 11h 10h din n din m din n din m col. add1 80h col. add2 row add1 row add2 row add3 twb tprog twb tdbsy col. add1 col. add2 row add1 row add2 row add3 twc read staus command twhr tprog 0~7 80h address & data input 11h col add 1,2 & row add 1,2,3 2112 byte data) a0 ~ a11 : valid a12 ~ a17 : valid a18 : fixed high a19 ~ a28 : valid note tadl tadl note : any command between 11h and 81h is prohibited except 70h and ffh 81h address & data input 10h 70h ba53f20d-20c iz[[]vuuu[vywwtwtwgwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 43 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cmd addr addr addr addr addr cmd addr addr addr addr addr din din din din din din din din cmd cmd 80h c1 a c2 a d0 a r3 a r2 a r1 a d1 a ... dn a 11h 80h c1 b c2 b d0 b r3 b r2 b r1 b d1b a ... dn b 10h cycle type dqx sr[6] cycle type dqx sr[6] a tadl tadl tadl tipbsy tadl tprog figure 21 : multiple plane page program (onfi 1.0 protocol) notes : c1 a -c2 a column address for page a. c1 a is the least significant byte. r1 a -r3 a row address for page a. r1 a is the least significant byte. d0 a -dn a data to program for page a. c1 b -c2 b column address for page b. c1 b is the least significant byte. r1 b -r3 b row address for page b. r1 b is the least significant byte. d0 b -dn b data to program for page b. same restrictions on address of pages a and b, and allowed commands as figure 20 apply *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 44 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash figure 22: multiple plane copy back program (traditional protocol) note: the figure refers to x8 case. please refer to section 1.4 for address remapping rules for the x16 case *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 45 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 00h cle we ale re iox c1 a c2 a r1 a r2 a r3 a 35h 00h c1 b c2 b sr[6] a t r r1 b r2 b r3 b 35h t r 85h cle we ale re iox c1 c c2 c r1 c r2 c r3 c 11h 85h c1 d c2 d sr[6] a t ipbsy r1 d r2 d r3 d 10h t prog figure 23: multiple plane copy back read (onfi 1.0 protocol) notes: c1 a -c2 a column address for page a. c1 a is the least significant byte. r1 a -r3 a row address for page a. r1 a is the least significant byte. c1 b -c2 b column address for page b. c1 b is the least significant byte. r1 b -r3 b row address for page b. r1 b is the least significant byte. figure 24: multiple plane copy back program (onfi 1.0 protocol) notes: c1 c -c2 c column address for page c. c1 a is the least significant byte. r1 c -r3 c row address for page c. r1 a is the least significant byte. d0 c -dn c data to program for page c. c1 d -c2 d column address for page d. c1 b is the least significant byte. r1 d -r3 d row address for page d. r1 b is the least significant byte. d0 d- dn d data to program for page d. same restrictions on address of pages c and d, and allowed commands as figure 21 apply *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 46 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash two-plane block erase operation figure 25: multiple plane block erase (traditional protocol) note: the figure refers to x8 case. please refer to section 1.4 for address remapping rules for the x16 case row address block erase setup command1 block erase setup command2 erase confirm command read status command busy row address ex.) address restriction for two-plane block erase operation ale cle ce re r/b i/ox we r/b i/o0~7 twc 60h 60h row add1,2,3 row add1,2,3 a12 ~ a17 : fixed low a18 : fixed low a19 ~ a28 : fixed low a12 ~ a17 : fixed low a18 : fixed high a19 ~ a28 : valid address address 60h 70h d0h 60h d0h 70h i/o0 row add1 row add1 row add2 row add2 row add3 row add3 twc twb tbers tbers twhr i/o 1 = 0 successful erase i/o 1 = 1 error in plane ba53f20d-20c iz[[]vuuu[vywwtwtwgwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 47 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 60h cle we ale re iox r1 a r2 a r3 a d1h 60h r1 b r2 b sr[6] t iebsy r3 b d0h t bers figure 26: multiple plane block erase (onfi 1.0 protocol) notes: r1 a -r3 a row address for block on plane 0. r1 a is the least significant byte. r1 b -r3 b row address for block on plane 1. r1 b is the least significant byte. same restrictions on address of blocks on plane 0(a) and 1(b) and allowed commands as figure 24 apply *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 48 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash 90h cle we ale re io0~7 20h 4fh t 4eh 46h whr 49h trea figure 27: id read figure 28: onfi signature timing diagram 90h cle ce we ale re i/ox 00h trea adh device code 4th cyc. 5th cyc. 3rd cyc. tar read id command address 1 cycle maker code device code read id operation ba53f20d-240c i[[][wwtwtwwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 49 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cmd cmd dout dout dout cmd dout 30h d0 31h ... dn 31h d0 cycle type dqx sr[6] trr as defined for read trr twb tr twb tcbsyr twb tcbsyr figure 30: sequential read cache timings, start (and continuation) of cache operation figure 29: reset operation timing ff t rst we ale cle re# dq7:0 rb# ba53f20d-240c i[[][wwtwtwwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 50 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash figure 31: "random" read cache timings, st art (and continuation) of cache operation figure 32 : read cache timings, end of cache operation *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 51 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash vcc vth vcc(min) 100u smax invalid 0v ce v il v operation 5ms max ih v il wp readybusy dont care dont care dont care vcc(min) v th figure 33: power on and data protection timings note: v th = 1.2 volt for 1.8 volt supply devices: 1.8 volt for 3.0 volt supply devices. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 52 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash rp value guidence rp (min. 1.8v part) = = where il is the sum of the input currnts of all devices tied to the r/b pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 1.8v, ta = 25c, c l =30pf rp vs tr, tf & rp vs ibusy vcc (max.) - v ol (max.) 1.85v p$?, l , ol + ?, l rp ibusy busy ready v cc v oh tr tf v ol v ol : 0.4v, v oh : 2.4v vcc 300n 200n 100n gnd device open drain output r/b c l 1.8v device - v ol : 0.1v. v oh : vcc-0.1v 2.7v device - v ol : 0.4v. v oh : vccq-0.4v 3.3v device - v ol : 0.4v. v oh : 2.4v tf 1.70 1.70 1.70 1.70 30 tr 3m 2m 1m ibusy [a] tr,tf [c] 1k 2k 3k 4k ibusy 60 1.70 0.85 90 120 0.57 0.43 rp(ohm) 300n 200n 100n tf 2.3 2.3 2.3 2.3 30 tr 3m 2m 1m ibusy [a] tr,tf [c] 1k 2k 3k 4k ibusy 60 2.3 1.1 90 120 0.75 0.55 rp(ohm) 300n 200n 100n tf 1.8 1.8 1.8 1.8 50 tr 3m 2m 1m ibusy [a] tr,tf [c] 1k 2k 3k 4k ibusy 1.2 2.4 100 150 200 0.8 0.6 rp(ohm) @ vcc = 2.7v, ta = 25c, c l =30pf @ vcc = 3.3v, ta = 25c, c l =50pf rp (min. 2.7v part) = = vcc (max.) - v ol (max.) 2.5v p$?, l , ol + ?, l rp (min. 3.3v part) = = vcc (max.) - v ol (max.) 3.2v p$?, l , ol + ?, l 1.8v version 3.0v version figure 34: ready/busy pin electrical application ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 53 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash t 80h 10h ww we iox wp r/b t 80h 10h ww we iox wp r/b t 60h d0h ww we iox wp r/b t 60h d0h ww we iox wp r/b 00h cle we ale re io0-7 p1 r/b ... ... t r 1 p0 1 p1 0 p0 0 ech figure 35: program enabling / disabling through wp# handling figure 36: erase enabling / disabling through wp# handling figure 37: read parameter page timings ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 54 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cle ale we io0-7 re 70h sr twhr trea cle ale we io0-7 re 78h r1 r2 sr r3 twhr tar figure 38: read status timings figure 39: read status enhanced timings ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 55 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cle ale ce re r/b iox we column address row address twb column address row address tcbsyr 1 1 cle ale ce re r/b iox we tpcsby din n din m din n din m column address row address 10h din n din m 70h tprog 80h col. add1 col. add2 row. add1 row. add2 row. add3 15h 80h 15h 80h col. add1 col. add2 row. add1 row. add2 row. add3 tadl i/o q twc col. add1 col. add2 row. add1 row. add2 row. add3 twc twc figure 40: cache program ba53f20d-240c iz[[x]vxuxuxu[vywxwtxwtwgxwaw
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 56 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cle ale ce re r/b iox we column address row address twb twc column address row address tcbsy 1 1 cle ale ce re r/b iox we tdbsy 11h din n din m col. add1 80h col. add2 row add1 row add2 row add3 col. add1 81h col. add2 row add1 row add2 row add3 15h din n din m column address row address twc column address row address tprog tdbsy 11h din n din m col. add1 80h col. add2 row add1 row add2 row add3 col. add1 81h col. add2 row add1 row add2 row add3 10h din n din m twb tadl tadl twb i/o 70h 80h address input data input 11h 81h address input data input 15h command input a13~a17:fixedlow a18:fixedlow a19~a31:fixedlow a13~a17:valid a18:fixedlow a19~a31:fixedlow t dbsy return to 1 repeat a max of 63 times 80h address input data input 11h 81h address input data input 10h command input a13~a17:fixedlow a18:fixedlow a19~a31:fixedlow a13~a17:valid a18:fixedlow a19~a31:fixedlow t dbsy t prog t pcbsy ry/by ry/by 1 1 q figure 41: multi-plane cache program (traditional protocol) note: 1) the figure refers to x8 case. please refer to section 1.4 for address remapping rules for the x16 case 2) read status register (70h) is used in the fi gure. read status enhanced (78h) can be also used *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 57 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash cle ale ce re r/b iox we column address row address twb twc column address row address tcbsy 1 1 cle ale ce re r/b iox we tdbsy 11h din n din m col. add1 80h col. add2 row add1 row add2 row add3 col. add1 80h col. add2 row add1 row add2 row add3 15h din n din m column address row address twc column address row address tprog tdbsy 11h din n din m col. add1 80h col. add2 row add1 row add2 row add3 col. add1 80h col. add2 row add1 row add2 row add3 10h din n din m twb tadl tadl twb i/o f1h 80h address input data input 11h 80h address input data input 15h command input a13~a17:fixedlow a18:fixedlow a19~a31:fixedlow a13~a17:valid a18:fixedlow a19~a31:fixedlow t dbsy return to 1 repeat a max of 63 times 80h address input data input 11h 80h address input data input 10h command input a13~a17:fixedlow a18:fixedlow a19~a31:fixedlow a13~a17:valid a18:fixedlow a19~a31:fixedlow t dbsy t prog t pcbsy ry/by ry/by 1 1 q figure 42: multi-plane cache program (onfi protocol) note: 3) the figure refers to x8 case. please refer to section 1.4 for address remapping rules for the x16 case 4) read status register (70h) is used in the figure. read status enhanced (78h) can be also used *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 58 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash ' $ ',( $ h % / . ( ( & &3 $ 7 package mechanical table 29: 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.10 0.05 0.15 0.004 0.002 0.006 a2 1.00 0.95 1.05 0.039 0.037 0.041 b 0.22 0.17 0.27 0.009 0.007 0.001 c 0.10 0.21 0.004 0.008 cp 0.08 0.003 d 12.00 11.90 12.10 0.472 0.468 0.476 e 20.00 19.80 20.20 0.787 0.779 0.795 e1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 - - 0.020 - l 0.60 0.50 0.70 0.024 0.020 0.028 a 305305 figure 43. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw_
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 59 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash x8 r r r r/b4# r/b3# r/b2# r/b1# re# ce1# ce2# r vcc vss ce3# ce4# cle ale we# wp# r r r r r r/vss r r r io7 io6 io5 io4 r r/vcc r vcc vss r r/vcc r io3 io2 io1 io0 r r r r/vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 x8 figure 44: onfi 1.0 tsop and wsop connection (x8 multi ce# / multi rybyconfiguration) (*) notes: 1) tsop48 "onfi" is supported only for x8 i/o configuration 2) pins marked in red are used in case a quad stack die is implemented with separated ryby and ce# pins. if this is not the case, ce# for the stack is pin 9, and ryby# for the stack is pin 7, and pins marked in red bold are reserved ("r") 3) this package is supported only if die is mounted over package frame 7.1 power consumptions and pin capacitance for allowed stacking configurations table 28 reports the power consumptions related to the single ch ip case. when multiple dice are stacked in the same package the power consumption of the stack will increase according to the nr of chips of it. as an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption depends on the nr of chips concurrently executing different operations. similarly, table 26 reports the pin capacitance for the single chip case. when multiple dice are stacked in the same pack- age the pin/ball capacitance for the single input and the sing le input/output of the combo package must be calculated based on the number of chips sharing that input or that pin/ball. *ba53f20d-240c* b34416/177.179.157.84/2010-10-08 10:08
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 60 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash ce dont-care 80h start add.(5cycle) data input 10h data input cle ce we ale i/ox ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 8 application notes and comments 8.1 system interface using ce# don't care to simplify system interface, ce# may be un-asserted during data loading or sequential data-reading as shown below. by operating in this way, it is possible to connect nand flash to a microprocessor. contrary to standard nand, ce# don't care devices do not allow sequential read function. figure 45: program operation with ce# don't-care. figure 46: read operation with ce# don't-care. *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 61 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash data buffer memory of the controller n page ffh (2) (3) data ffh failure (1) th n page th 8.2 system bad block replacement over the lifetime of the device additional bad blocks may develop. in this case each bad block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will return "fail" after read status register. the failure of a page program operation does not affect the data in other pages in the same block, thus the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. refer to table 30 and figure 47 for the recommended procedure to follow if an error occurs during an operation. table 30: block failure figure 47 : bad block replacement note: 1. an error occurs on n th page of the block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. n th page of block a which is in controller buffer memory is copied into n th page of block b 4. bad block table should be updated to prevent from erasing or programming block a operation recommended procedure erase block replacement program block replacement read ecc *ba53f20d-240c* iz[[x]vx^^ux^`ux\^u_[vywxwtxwtw_gxwaw`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcw m_4828539:w p_0000001w p_0000001 rev 1.4 / oct. 2010 62 1 h27(u_s)4g8_6f2d 4 gbit (512m x 8 bit) nand flash <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh 8.3 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased(ffh). the bad block information is written prior to shipping. any block where the 1st byte in the spare area of the 1st or 2nd th page (if the 1st page is bad) does not co ntain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recog- nize the bad blocks based on the original information it is recommended to create a bad block table following the flow- chart shown in figure 48. the 1st block, which is placed on 00h block address is guaranteed to be a valid block. figure 48: bad block management flowchart note : 1. check ffh at 1st byte in the spare area of the 1st or 2nd th page (if the 1st page is bad). *ba53f20d-240c* b34416/177.179.157.84/2010-10-08 10:09

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